The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a saddle type transistor having a saddle type fin.
A typical cell in a three-dimensional structure for use in a dynamic random access memory (DRAM) cell includes a fin structure, a recess channel structure, and a saddle type structure. The saddle type structure includes the fin structure and the recess channel structure in combination.
FIG. 1A illustrates a perspective view showing a method for fabricating a typical saddle type transistor, and FIG. 1B illustrates a plan view of a fin mask. Referring to FIGS. 1A and 1B, an isolation structure 12 is formed in a substrate 11 using a shallow trench isolation (STI) process. Thus, an active region 11A having a major axis and a minor axis is defined. A fin mask 13 is formed over the substrate structure. Saddle type fins 14 are formed by etching using the fin mask 13. The etching for forming the saddle type fins 14 may include etching the isolation structure 12 using the fin mask 13 and then etching the active region 11A, or etching the active region 11A and then etching the isolation structure 12. The fin mask 13 is removed, and although not illustrated, a gate oxide layer, a gate electrode, and source/drain are formed to complete a saddle type transistor.
The typical method as described above uses the line type fin mask 13 to form the saddle type fins 14. However, in the typical method, the active region 11A is exposed by the line type fin mask 13 at regions predetermined for forming the saddle type fins 14 as well as at the ends of the active region 11A along the major axis. Thus, dummy saddle type fins 14A may be formed. The dummy saddle type fins 14A may be formed in an active region that will be connected to a storage node. Thus, leakage of the storage node and capacitance of the gate may be increased, deteriorating performance of the transistor.